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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC141622
Advance Information
Advanced Comb Filter-II (AFC-II)
The Advanced Comb Filter-II is a video signal processor for VCRs and TVs. It's function is to separate the Luminance Y and Chrominance C signals from the NTSC composite video signal. The ACF-II minimizes dot-crawl and cross-color. A built-in PLL provides a 4xfsc clock from either an NTSC subcarrier signal or a 4xfsc input. This allows a video signal input of an extended frequency bandwidth. The built-in vertical enhancer circuit improves the quality of the Luminance Y signal. The built-in A/D and D/A converters allow easy connection to analog video circuits. * * * * * * * * * Built-in High Speed 8-Bit A/D Converter Two Line Memories (1820 Bytes) Advanced Comb-II Process Vertical Enhancer Circuit Two High Speed 8-Bit D/A Converters 4xfsc PLL Circuit Built-in Clamp Circuit Digital Interface Mode On-Chip Reference Voltage Regulator for A/D Converter
P SUFFIX 48-LEAD QFP CASE 898
ORDERING INFORMATION
MC141622FU Quad Flat Package (QFP)
PIN ASSIGNMENT
D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 36 35 34 33 32 31 30 29 28 27 26 25 D3 D2 D1 D0 BK VH GND(D) VCC(D) FSC NC NC NC 37 38 39 49 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
TE1 TE0 MODE1 MODE0 CLK(AD) GND(D) VCC(D) CLC CLout Vin RBT RTP
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1 1/97 TN97012000
(c) Motorola, Inc. 1997 MOTOROLA
PCO OVCC BIAS FILIN GND(DA) Y out VCC(DA) C out REF(DA) I bias GND(AD) VCC(AD) NC = NO CONNECTION
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BLOCK DIAGRAM
D4
D5
D6
D7
C0
C1
C2
C3
C4
C5
C6 26
36
35
34
33
32
31
30
29
28
27
25
C7
D3 37 PORT D2 38 D1 39 D0 40 BK 41 VH 42 GND(D) 43 VCC(D) 44 FSC 45 NC 46 NC 47 NC 48 1 PCO 2 OVCC 3 BIAS 4 FILIN 5 GND(DA) 6 Yout CLKBUF CONTROL LOGIC CLAMP ADAPTIVE VERTICAL ENHANCER ACF-II PROCESSING CONTROL LOGIC CLKBUF 1H 1H PORT
24 TE1 23 TE0 22 MODE1 21 MODE0 20 CLK(AD) 19 GND(D) 18 VCC(D) 17 CLC 16 CLout 15 Vin ADC DAC DAC Ibias 14 RBT 13 RTP
MODE
CLOCK GEN
7 VCC(DA)
8 Cout
9 REF(DA)
10 I bias
11 GND(AD)
12 VCC(AD)
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ABSOLUTE MAXIMUM RATINGS*
Characteristic DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current (per pin) DC Output Current (per pin) Power Dissipation Storage Temperature Symbol VCC Vin Vout Iin Iout PD Tstg Value - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 750 - 65 to + 150 Unit V V V mA mA mW C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
GENERAL ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C, Unless Otherwise Noted)
Characteristic Supply Voltage Operating Supply Current Operating Power Dissipation Ambient Operating Temperature NOTE: 1. At normal mode. Symbol VCC ICC PD TA Min 4.75 -- -- - 20 Typ 5.0 115 575 -- Max 5.25 140 735 75 Unit V mA mW C 1 1 Notes
CLOCK INPUT ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C, Unless Otherwise Noted)
Characteristic Subcarrier Input Frequency Clock Frequency FSC Clock Input Level High Level Input Voltage Low Level Input Voltage Clock Duty Cycle CLK(AD) CLK(AD) CLK/CLK(AD) Symbol fc CLK Vfc VICH VICL Dty Min -- -- 1 3.15 -- 45 Typ 3.579545 14.31818 -- -- -- 50 Max -- -- -- -- 1.1 55 Unit MHz MHz V p-p V V % Notes 1 2 3 4 4 4
NOTES: 1. Color subcarrier input [FSC = (455/2)fh] locked on the burst signal of the input video signal. AC coupling input by external capacitor. 2. The internal circuit operates by four times clock using FSC-pin input at normal (FSC) mode. 3. Sine wave input. 4. CLK(AD) is available only during digital input comb filter mode.
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ADC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic Resolution Integral Nonlinearity Differential Nonlinearity Top Reference Level Bottom Reference Level Maximum Analog Input Range During Self Reference Symbol -- INL DNL VTPS VBTS Vins Min -- -- -- 4.5 1.45 2.85 Typ -- 1.5 0.5 4.6 1.55 3.05 Max 8 2.5 1.0 4.7 1.65 3.25 Unit Bits LSB LSB V V V p-p
DIGITAL ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic High Level Input Voltage Low Level Input Voltage Input Leakage Current [Vin = VCC(D) or GND(D)] MODE0, MODE1, TE0, TE1, BK, C0 - C7, D0 - D7 MODE0, MODE1, TE0, TE1, BK, VH, C0 - C7, D0 - D7 MODE0, MODE1, TE0, TE1, BK VH C0 - C7, D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 C0 - C7, D0 - D7 Symbol VIH VIL Iinl tds tdh tr tf tdl Min 3.15 -- -- 0 20 -- -- -- Typ -- -- -- -- -- -- -- 45 Max -- 1.1 10 -- -- 10 10 -- Unit V V A ns ns ns ns ns
Data Setup Time (at Digital Input Comb Filter Mode) Data Hold Time (at Digital Input Comb Filter Mode) Data Input Rise Time (at Digital Input Comb Filter Mode) Data Input Fall Time (at Digital Input Comb Filter Mode) Output Data Delay (at Digital Input/Output Comb Filter Mode)
FILTERING CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic Y/C Separation Band-Pass Filter Bandwidth (at - 3 dB) Symbol -- -- Min 40 -- Typ -- 0.75 Max -- -- Unit dB MHz
DAC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic Resolution Integral Nonlinearity Differential Nonlinearity Analog Output Voltage, Yout Analog Output Voltage, Cout Full Scale Voltage, Yout Full Scale Voltage, Cout Zero Scale Voltage, Yout Zero Scale Voltage, Cout Output Impedance Symbol -- INL DNL VYO VCO VYFS VCFS VYZS VCZS ZO Min -- -- -- 1.1 1.1 1.3 1.3 0.1 0.1 -- Typ -- -- -- 1.2 1.2 1.5 1.5 0.3 0.3 100 Max 8 1 0.5 1.3 1.3 1.7 1.7 0.5 0.5 300 Unit Bits LSB LSB V p-p V p-p V V V V
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CLAMP CIRCUIT CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic Clamp Mode Output Voltage* * At using the clamp circuit when connecting Vin - CLout. Symbol Vclys Min -- Typ 1.6 Max -- Unit V
BK/VH CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic BK Switching Time, at Normal Mode VH Switching Time, at Normal Mode Symbol Min -- -- Typ 9 9 Max -- -- Unit Clock Clock
VERTICAL ENHANCER LEVEL CHARACTERISTICS (VCC = 5.0 V, TA = 25C 3C)
Characteristic Noise Slice Level, at Normal Mode White Enhance Level, at Normal Mode Black Enhance Level, at Normal Mode Symbol Min 0 0 0 Typ -- -- -- Max 15 15 15 Unit bit bit bit
GENERAL SIGNAL DELAY (VCC = 5.0 V, TA = 25C 3C)
Characteristic Normal Mode, 938 Clock Symbol Min -- Typ 65.511 Max -- Unit s
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MC141622 5
CLK(AD)
AD INPUT
N-1
N N+1 N+2 N+3 N+4 N+5
OUTPUT DATA (C0 - C7) tdl
N-3
N-2
N-1
N
N+1
N+2
= Sampling Point
Figure 1a. A/D Converter Timing Diagram (During Digital Input Comb Filtering Mode)
CLOCK
INPUT DATA (D0 - D7) tds tdh tr tf
Figure 1b.Digital Signal Input Timing Diagram (During Digital Input Comb Filtering Mode)
CLOCK
OUTPUT DATA (C0 - C7, D0 - D7) tdl N-2 DA OUTPUT (Yout, Cout)
N
N+1
N+2
N+3
N+4
N+5
N+3 N-1 N N+2 N+1 N+4
Figure 1c. Output Signal Timing Diagram (During Digital Output Comb Filtering Mode) Figure 1. Timing Diagrams
Clamp Circuit Characteristics (VCC = 5.0 V, TA = 25C 3C) Clamp Mode Output Voltage, Vcly (Non-input when connecting Vin - CLout) Vcly = (VTP - VBT) (N + 1) / 256 + VBT 50 mV where N = Clamp Code Input (N < 255)
* If the calculated value of the output voltage, Vcly > Vclys, then Vcly = Vclys * Clamp Value N is fixed, N = 4.
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PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21, 22 23, 24 25 26 - 28 29 30 - 32 33 34 - 40 41 42 43 44 45 46 - 48 Pin Name PCO OVCC BIAS FILIN GND(AD) Yout VCC(DA) Cout REF(DA) Ibias GND(AD) VCC(AD) RTP RBT Vin CLout CLC VCC(D) GND(D) CLK(AD) MODE0, MODE1 TE0, TE1 C7 C6 - C4 C3 C2 - C0 D7 D6 - D0 BK VH GND(D) VCC(D) FSC NC Phase comparator output. Power supply for VCO. Reference for VCO. Generally connected to GND(D) through an external resistor. VCO controlled voltage input. Generally connected to PCO through an external loop filter. GND for D/A converter. Luminance signal output. Power supply for D/A converter. Chrominance signal output. Reference for D/A converter. Generally connected to GND(DA) through a multilayer ceramic capacitor (0.1 F). Bias circuit current control for A/D, D/A converters. Generally connected to GND(DA) through an external resistor. GND for A/D converter. Power supply for A/D converter. Top reference for A/D converter. Supplies top reference voltage internally. Bottom reference for A/D converter. Supplies bottom reference voltage internally. A/D converter input. Voltage output for clamp. Clamps an input signal by connecting with Vin and inputting the video signal by ac coupling. Clamp time constant setting pin. Power supply for digital circuit. GND for digital circuit. CLK input for A/D converter. Available only during digital input comb filtering mode and a portion of test mode. Input level is CMOS level. Mode input. GND level during normal (FSC) mode. Test mode input. Generally GND level. Digital interface 1, input/output. Generally VCC(D) level. Digital interface 1, input/output. Generally GND(D) level. Digital interface 1, input/output. Generally VCC(D) level. Digital interface 1, input/output. Generally GND(D) level. Digital interface 2, input/output. Generally VCC(D) level. Digital interface 2, input/output. Generally GND(D) level. Non-color signal processing mode. Generally GND(D) level. Vertical enhancer circuit mode. Generally GND(D) level. GND for digital circuit. Power supply for digital circuit. CLK input. AC coupling input by external capacitor. Normal (fsc) mode: Subcarrier. Normal (4xfsc) mode: 4* Subcarrier. No connection. Generally GND level. Function
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MC141622 7
Figure 2 shows the I/O signals of the Advanced Comb Filter-II.
PCO OVCC BIAS FILIN GND(DA) Yout VCC(DA) Cout REF(DA) I bias GND(AD) VCC(AD)
1 2 3 4 5 6 7 8 9 10 11 12
D3 D2 D1 D0 BK VH GND(D) VCC(D) FSC NC NC NC
37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7
MC141622
TE1 TE0 MODE1 MODE0 CLK(AD) GND(D) VCC(D) CLC CLout Vin RBT RTP
DIGITAL
DIGITAL
PLL
D/A CONVERTER
A/D CONVERTER
Figure 2. Pin Assignment
DEVICE DESCRIPTION
INTRODUCTION The Advanced Comb Filter-II (ACF-II) is a high-performance HCMOS digital filter with built-in A/D and D/A converters. The basic function of the chip is the separation of the Luminance Y and Chrominance C signals from the NTSC composite video signal. The ACF-II minimizes the problems often generated by Y/C separation such as dot-crawl and cross-color. It uses a 14.3 MHz clock that allows an extended frequency bandwidth video signal to be input. This Y/C separation is realized by the digital advanced comb filters. The built-in 4xfsc PLL circuit allows a subcarrier signal input, from which a 4xfsc clock is generated for video signal processing. This allows a video signal input of an extended frequency bandwidth. The built-in vertical enhancer circuit can enhance the Luminance Y signal. The built-in A/D and D/A converters allow easy connection to analog video circuits. The second block contains the Advanced Comb Filter-II algorithm. The digital data from the A/D converter is processed by the algorithm of the Advanced Comb Filter-II. The composite video is filtered by the band-pass filter (BPF) and separated into the Luminance Y and Chrominance C signals. The third block is the vertical enhancer circuit block. This vertical enhancer emphasizes the picture outline of the vertical direction. The fourth block is the digital-to-analog conversion block. Two 8-bit D/A converters convert the luminance and chrominance into analog outputs. The conversion frequency is four times the subcarrier signal (14.3 MHz). The chrominance analog output is biased with a dc offset of half the value of the DA converter reference. The fifth block is a 4xfsc CLK generation circuit. This block generates four times the subcarrier signal and phase locks the inputting subcarrier on FSC pin. A/D Converter The composite video signal input is converted to the digital code by the high speed 8-bit A/D converter. The A/D converter reference has a self-bias function which generates VTP = 4.6 V, VBT = 1.55 V. This allows the A/D converter to function without an external reference circuit. Clamp Voltage Regulating Circuit The clamp voltage regulating circuit sync tip clamps the input signal when the Vin pin is connected to the CLout pin and the video signal is input using ac coupling. It compares the
ADVANCED COMB FILTER-II DESCRIPTION The simplified block diagram of the Advanced Comb Filter-II chip is shown at the beginning of this data sheet. There are five major functions represented in this block diagram. The first block is the A/D conversion block. The high speed 8-bit binary analog-to-digital converter converts the incoming analog video signal to an 8-bit binary data stream. The conversion frequency is 14.3 MHz which is four times the color subcarrier frequency.
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digital value of the clamp level ($04) with the A/D converter output code. The clamp voltage from CLout is then output. Advanced Comb Filter-II The Advanced Comb Filter-II is a digital comb filter developed for use in the NTSC system. The vertical correlation circuit provides high picture quality and high resolution and requires no adjustment for its Y/C separation. The clock frequency is 14.3 MHz, which is four times the NTSC subcarrier. The BK pin can be used to select between the composite signal output without Y/C separation and the Y/C signal output. Table 1 shows the relationship of the BK pin and each output. Table 1. BK Function
BK Pin L H Yout Luminance Composite Cout Chrominance Chrominance
crawl. This block does not emphasize horizontal and vertical sync signals. Table 2 shows the relationship of the VH pin and the vertical enhancer function. The coring characteristics of the vertical enhancer circuit can be set up on the digital port at the normal mode. Table 2. VH Function
VH Pin L H Vertical Enhancer On Off
D/A Converter The luminance and chrominance signals separated in the advanced comb filtering portion are converted to analog signals by two 8-bit D/A converters. The output voltage range is from 0.3 V to 1.5 V, 1.2 Vp-p. The sampling clock of the D/A converter is 14.3 MHz. Clock Generation Circuit The internal PLL can be selected to operate in either of two modes; an X4 mode used to generate a 4xfsc clock from a normal NTSC color subcarrier, and an X1 mode when a 4xfsc signal is available.
Adaptive Vertical Enhancer Circuit The vertical enhancer circuit is used the adaptive enhanced processing using two line memories. The adaptive LPF of the vertical enhancer circuit minimizes noise and dot-
OUT
WHITE IN BLACK
OUT WHITE LEVEL (C4 - C7) (0 - 15 STEP) IN
C7 C3 D7 L L L L L L L L H H H H H H H H
C6 C2 D6 L L L L H H H H L L L L H H H H
C5 C1 D5 L L H H L L H H L L H H L L H H
C4 C0 D4 L H L H L H L H L H L H L H L H Level L l 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUT
OUT
IN NOISE LEVEL (D4 - D7) (0 - 15 STEP) BLACK LEVEL (C0 - C3) (0 - 15 STEP)
IN
Figure 3. Coring Characteristics
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OPERATING MODES The Advanced Comb Filter-II can be operated in any of four modes. These modes are fixed by a digital code input into MODE0 and MODE1. The descriptions of the four types of operating modes are: Normal (fsc) Mode This mode is for the normal Y/C separation. The video signal input to the A/D converter is separated into its Y and C components and output as analog information from the D/A converter outputs. The clamp circuit operates as sync tip clamp by connecting CLout with Vin, and clamps the input video signal to the fixed value $04. The coring characteristics of the vertical enhancer circuit can be set up on the digital port. This mode is used when an NTSC color subcarrier is used to generate a 4xfsc using the internal PLL. Normal (4xfsc) Mode This mode is for the normal Y/C separation. The video signal input to the A/D converter is separated into its Y and C components and output as analog information from the D/A converter outputs. The clamp circuit operates as sync tip clamp by connecting CLout with Vin, and clamps the input video signal to the fixed value $04. The coring characteristics of the vertical enhancer circuit can be set up on the digital port. In this mode an external 4xfsc CLK is input on the FSC pin. Digital Input Comb Filtering Mode In this mode, the comb filter is used as two separate blocks; the A/D converter portion, and the filter and D/A portion. This mode can re-input and filter converted digital data outputs by the A/D converter after arbitrarily being digitally processed by external circuits. The converted digital data outputs into C0 - C7. Moreover, the data input into D0 - D7 is filtered by the ACF-II algorithm, and is output as an analog signal from Yout and Cout. The two blocks can operate independently with different frequency and phase clock signals. The CLK(AD) pin is the clock input to the A/D converter block and the CLK pin the clock source (4xfsc) for the filter and D/A converters. At this time, the clamp circuit works as sync tip clamp when CLout is connected to Vin, and clamps the input video signal to the internally fixed digital value ($04). Digital Output Comb Filtering Mode This mode outputs digital values of the luminance and chrominance signals in addition to functioning as a standard analog output Y/C separator. This allows arbitrary digital processing of the filter-processed Y and C digital outputs by an external circuit. It interfaces with an analog circuit easily, since both analog Y and C signals are output at the same time. The video signal input to the A/D converter is converted to digital data, and forwarded to the filter portion. The Y/C separated data from the filter portion is output from Yout and Cout after the D/A conversion. At the same time, the filter portion output is also forwarded to the digital interface and the luminance digital value is output from C0 - C7 and the chrominance digital value is output from D0 - D7. With this mode, the clamp circuit works as a sync tip clamp with CL out connected to Vin, and clamps the input video signal internally to the fixed digital value ($04). This mode operates with an external 4xfsc CLK which is input on the FSC pin. Table 3 shows the relationship between the MODE pin and MODE condition.
Table 3. Operating MODE Switching Function
Mode Normal (fsc) Mode Normal (4xfsc) Mode Digital Input Comb Filtering Mode Digital Output Comb Filtering Mode MODE1 L L H H MODE0 L H L H
APPLICATION DESIGN CONSIDERATIONS VCC, GND To maximize the performance of the MC141622, noise should be kept to a minimum. Good printed circuit board design will enhance the operation of the MC141622. Separate analog and digital grounds will reduce noise and conversion errors. In addition, separate filters on analog VCC and digital VDD will also help to minimize noise and conversion errors. Sufficient decoupling and short leads will also improve performance. When designing mixed analog/digital printed circuit boards, separate ground planes for digital ground and analog ground should be employed. Large switching currents generated by digital circuits will be amplified by analog circuitry and can quickly make a circuit unusable. Care should be taken to ensure analog ground does not inadvertently become part of the digital ground. The analog and digital grounds should be connected together at only one point. This is usually at or near where power enters the printed circuit board. Additionally, when interconnecting several printed circuit boards together, care must be taken to ensure that cabling does not interconnect digital and analog grounds together to produce a path for digital switching currents through analog ground. When using any device with the performance and speed of the MC141622, ground planes are essential. Loosely interconnected traces and/or random areas of ground strewn around the printed circuit board are inadequate for high performance circuitry. While distribution of VDD and VCC can be done by bussing, to do so with the ground system is disastrous. A 1-inch long conductor is an 18 nH inductor. The cross sectional area of the conductor affects the exact value of the inductance, but for most PCB traces this is approximately correct. If the ground system is composed of traces or clumps of ground loosely interconnected, it will be inductive. The amount of inductance will be proportional to the length of the conductors making up the ground. This inductance cannot be decoupled away. It must be designed out. A CMOS device exhibits a characteristic input capacitance of about 10 pF. If this gate is driven by a digital signal that switches 2.5 V in a period of 5 ns, the equation for the average current flowing during the switching time will be: IAV = Cdv/dt. A voltage change of 2.5 V in 5 ns requires an average current of 5 mA. If we assume a linear ramp starting from zero, the total change in current will be 10 mA. The change in current per nanosecond per gate can be found by dividing the change in current by the time 10 mA/5 ns = 2 mA/ns. For a device with 16 outputs driving one gate for each output, di/dt = 16 x 2 mA/ns = 32 mA/ns.
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If the above 1-inch wire is in this current path, then the voltage dropped across it can be found from the formula V = Ldi/dt = 18 nH x 32 mA/ns = 0.576 V. If the inductor is in the ground system, it is in the signal path. The voltage generated by the switching currents through this inductor will be added to the signal. At best it will be superimposed on the analog signal as unwanted noise. At worst, it can render the entire circuit unusable. Even the digital signal path is not immune to this type of signal. It can false trigger clock circuits causing timing errors, confuse comparator type circuits, and cause digital signals to be misinterpreted as wrong values. When laying out the PCB, use electrolytic capacitors of sufficient size at the power input to the printed circuit board. 47 F tantalum capacitors are recommended. Adding low ESR (effective series resistance) decoupling capacitors of about 0.1 F capacitance across VCC and/or VDD at each device will help reduce noise in general and ESD (electrostatic discharge) susceptibility. Connect the high-capacity and high-frequency capacitors as close as possible to all analog VCC, digital VDD, and ground pins. Implementation of a good ground plane ground system can all but eliminate the type of noise described above. To summarize, use sufficient electrolytic capacitor filtering, make separate ground planes for analog ground and digital ground, tie these grounds together at one and only one point, keep the ground planes as continuous and unbroken as possible, use low ESR capacitors of about 0.1 F capacitance on VCC and VDD at each device, and keep all leads as short as possible. Vin In order to prevent flyback noise on the video input, it is necessary to keep the bandwidth to less than 1/2 the clock frequency by using an area filter. Here the amplifier used as an input buffer needs a wide bandwidth and driving capability. Moreover, to minimize external noise effects, drive the Vin pin with a low impedance amplifier and keep the Vin pin as close as possible to the amplifier output. When using the built-in clamp circuit, connect CLout with Vin and input signals after ac coupling by using a high- performance, high frequency capacitor of 1 to 0.1 F. In this case, keep the Vin, CLout, coupling capacitor, and buffer- amplifier wiring as short as possible. Pay attention to the external noise and parasitic impedance. AD Reference Pin The RTP and RBT pins have a self-bias function that internally generates V TP = 4.6 V and V BT = 1.55 V. It acknowledges the AD converter analog input dynamic range. A stable performance can be achieved by applying a high- performance frequency capacitor as close as possible to the RTP and RBT pins and bypassing to GND(AD). A 0.1 F
multi-layer ceramic capacitor and a 10 F tantarum capacitor are recommended. CLC The CLC pin sets the clamp circuit speed with an external capacitor and resistor. Generally, the capacitor and resistor are arranged in a row and connected with GND(AD). Select a capacitor that minimizes the dielectric absorbing error. When the capacitor capacity is reduced, the shift speed of the video signal to VCC(AD) side is accelerated. If the resistor value is too small at this point, sagging will appear in the video signal. Also, if the capacitor's capacity is too large, the clamp speed will slow down; therefore, it is very important to pay attention to the setup of the resistor capacitor values. DA Reference REF(DA) is a DA converter reference decoupling pin for both the Yout and Cout. Bypass to GND(DA) by applying a high-performance, high-frequency capacitor as close to the pin as possible. A 0.1 F multilayer ceramic capacitor is recommended. Clock Input The clock frequency input is 3.58 MHz during normal (fsc) mode, and 14.31818 MHz during the other modes. The minimum input level is 1.0 Vp-p. It should be phase locked to the subcarrier of the video signal. The clock line should be wired with the shortest wire and be separated from other circuits to minimize cross coupling to other signals. The CLK(AD) pin is used only during digital input comb filtering mode; therefore, it should be at GND level unless the device is used in the digital input comb filtering mode. Ibias The Ibias pin is used to set up the bias current for the AD and DA converters. Connect an external resistor between the Ibias and GND(DA). Digital Input Comb Filtering Mode Connect CLK(AD) with the GND(D) when the AD converter is not being used. Connect D0 - D7 with GND(D), when the DA converter and filter are not being used. This is to eliminate any unnecessary operation of blocks which are not being used. At this point, make sure voltage is supplied to the VCC(AD), VCC(DA), and VCC(D). This eliminates latch-up during operating. Latch-Up The VCC(AD), VCC(DA), and VCC(D) pins connect to power supplies that are independent from each other. Therefore, latch-up may occur when the power is applied. To eliminate latch-up, apply power to VCC(AD), VCC(DA), and VCC(D) pins simultaneously.
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APPLICATION CIRCUIT
ADC GND DAC GND DIGITAL GND
+
VCC(D) 5V C 33 H 47 k x 4 ROTARY SW
TANTALUM CAPACITOR MULTI-LAYER CERAMIC CAPACITOR
+ 47
D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 F 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
0.1 F
VCC(A) 10 V
1.0 F
VIDEO IN
+
47 F
D3 0.1 F 10 k x 2 D2 D1 D0 BK VH
37 38 39 48 41 42 43 44 45 46 47 48 1 PCO 2 OVCC 3 BIAS 4 FILIN 5 GND(DA) 6 Y out 7
TE1 TE0 MODE1 MODE0 CLK(AD) GND(D) VCC(D) CLC CLout Vin RBT RTP 1.0 F 0.33 F 2 k CLK(AD) 750 k C2002 47 F
33 H
33 H
75
+
0.1 F
47 F
+ 0.1
F C2002
2.2 k
2.2 k
VCC(D) 5V CLK
33 H
SW
MC141622
19 18 17 16 15 14 13
8 1 4
GND(D) VCC(D) FSC NC NC NC
+ -
3 2 CLAMP LEVEL 2.2 k
MC14577
2 k
1 k GAIN ADJUST
510
510 k
A953
8
9 REF(DA)
10 11 GND(AD) I bias
12 VCC(AD)
VCC(DA) Cout
+ 0.1
10 F F
+
10 F
33 H VDD(A) 10 V 33 H 47 F
+ 0.1
200 F
0.1 F
43 k
10 k
VCC(D) 5V
0.1 F
+
0.1 F 8 1 4 3 2
9.1 k
33 H
+ + -
47 F
0.1 F
+
47 F VCC(A) (5 V) VCC(A) (10 V)
75 Yout
Vout MC7805CT
Vin
+ 0.1
10 F F
33 H 4.7 F
1/2MC14576 8 7 4 5 6
+
0.1 F
4.7 F GND
+
0.1 F
75 Cout
+ -
2/2MC14576
MC141622 12
MOTOROLA
EMI SUPPRESSION
When using ICs in or near television receiver circuits, EMI (electromagnetic interference) and subsequent unwanted display artifacts and distortion are probable unless adequate EMI suppression is implemented. A common misconception is that some offending digital device is the culprit. This is erroneous in that an IC itself has insufficient surface area to produce sufficient radiation. The device, while it is the generator of interfering signals, must be coupled to an antenna before EMI is radiated. The source for the EMI is not the IC which generates the offending signals but rather the circuitry which is attached to the IC. Potential EMI signals are generated by all digital devices. Whether they become a nuisance is dependent upon their frequency and whether they have a sufficient antenna. The frequency and number of these signals is affected by both circuit design within the IC and the manufacturing process. Device speed is also a major contributor of potential EMI. Because the design is determined by the anticipated application, the manufacturing process is fixed and the drive for speed ever increasing, the only effective point to implement EMI suppression is in the PC board design. The PC board usually is the antenna which radiates the EMI. The most efficient method of minimizing EMI radiation is to minimize the efficiency of this antenna. The most common cause of inadequate EMI suppression lies with the ground system of the suspected digital devices. As pointed out previously, di/dt transitions can be significant in digital circuits. If the di/dt transitions appear in the ground system and the ground system is inductive, the harmonics present in these transitions are a source of potential EMI signals. The unfortunate result of putting digital devices on a reactive ground system is guaranteed EMI problems. The area which should be addressed first as a potential EMI source is the ground. Without an adequate ground system, EMI cannot be effectively reduced by decoupling. If at all possible, the ground should be a complete unbroken plane. Figure 4 shows two examples of relieving ground around device pins. When relieving vias and plated through holes, large areas of ground loss should be avoided. When the relief pattern is equal to half the distance between pins, over-etching and process errors may remove ground between pins. If sufficient ground around enough pins is removed, the ground system can become isolated or nearly isolated "patches" which will appear inductive. If ground, such as the vicinity of an IC, must be removed, replace with a cross hatch of ground lines with the mesh as small as possible. If a single unbroken plane can be devoted to the ground system, EMI can usually be sufficiently suppressed by using ferrite beads on suspect EMI paths and decoupling with adequate values of capacitors. The value of the decoupling capacitor depends on the frequency and amplitude of the offending signals. Ferrite beads are available in a wide variety of shape, size and material to fit virtually any application. Choose a ferrite bead for desired impedance at the desired frequency and construct a low pass filter using one or more appropriate capacitors in a "L", "T" or "PI" arrangement. Use only capacitors of low inductive and resistive properties such as ceramic or mica. Install filters in series with each IC pin suspected of contributing offending EMI signals and as close to the pin as possible. Analysis using a spectrum analyzer can help determine which pins are suspect. Where PC board costs constrain the number of layers available, and if the EMI frequencies are far removed from the frequencies of operation, ferrite beads and decoupling capacitors may still be effective in reducing EMI emissions. Where only two (or in some cases, only one) layer is used, the ground system is always reactive and poses an EMI problem. If the offending EMI and normal operating frequency differ sufficiently, filtering can still work. An "island" is constructed in the ground system for the digital device using ferrite beads and decoupling capacitors as shown by the example in Figure 5. The ground must be cut so that the digital ground for the device is isolated from the rest of the ground system. Next choose a ferrite bead of the appropriate value. Install this bead between the isolated ground and the ground system. Install low pass filters in all suspect lines with the capacitor closest to the device pin connected to the isolated ground in all signal lines where EMI is suspect. Also cut the power to the device and insert a ferrite bead as shown in Figure 5. Finally, decouple the device between the power pin(s) and isolated ground pin(s) using a low inductive/resistive capacitor of adequate value. The methods described above will work acceptably when the EMI frequency and the frequency of operation of the device generating the EMI differ greatly. Where the EMI is disturbing the high VHF or UHF channels and the device generating the EMI is operating within the NTSC/PAL bandwidth, the energy contained in the harmonics generating the EMI is situated well above the operating frequency and suppressing this type of EMI poses no great problem. However, if the EMI is present on low VHF channels and/or the operation of the device is outside the NTSC/PAL bandwidth, such as a 2X pixel clock or 4xfsc oscillator, compromise between video quality and suppression complexity is usually required to obtain an acceptable solution. For those cases where the operating frequency of the device is very near the frequency of the EMI disturbance, careful attention to PCB layout, multiple layer PCB and even shielding may be necessary to obtain an acceptable design.
MOTOROLA
MC141622 13
WRONG
BETTER
Figure 4.
FERRITE BEAD
POWER
FERRITE BEAD
INPUT OR OUTPUT SIGNAL
CUT 0.1 F DECOUPLING LOW PASS FILTER
GROUND FERRITE BEAD
CUT
Figure 5.
MC141622 14
MOTOROLA
PACKAGE DIMENSIONS
FU SUFFIX 48-LEAD QFP CASE 898-01 B B P J -A-, -B-, -DG DETAIL A R W X DETAIL B K
0.200 (0.008)
DETAIL A L
48 1 37 S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A- , -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H- . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C- . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H- . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.48 (0.019). MILLIMETERS MIN MAX 11.90 12.10 11.90 12.10 2.05 2.55 0.20 0.40 2.00 2.30 0.80 BASIC 0.00 0.30 0.10 0.20 0.65 1.05 8.80 BASIC 13 REF 0.40 BASIC 0 7 0.13 0.30 14.90 15.70 14.90 15.70 0.65 REF 1.60 REF 5 REF INCHES MIN MAX 0.469 0.476 0.469 0.476 0.026 0.041 0.081 0.100 0.079 0.091 0.031 BASIC 0.000 0.011 0.005 0.008 0.026 0.041 0.346 BASIC 13 REF 0.016 BASIC 0 7 0.006 0.011 0.587 0.618 0.587 0.618 0.026 REF 0.063 REF 5 REF
A-B
S
0.200 (0.008) M C D 0.050 (0.002) D
-A-
-B-
12 13 24
25
0.200 (0.008)
M
L
B
V
HD
S
A-B
36
S
-DA 0.200 (0.008) M C A-B 0.050 (0.002) A-B S 0.200 (0.008)
M S
D
S
H A-B
S
D
S
M C -CH E Y
-HDETAIL B
DIM A B C D E G H J K L M P Q R S V W X Y
MOTOROLA
EEEE EEEE
D
M
Q
H A-B
S
D
S
SECTION B-B
ROTATED 90
MC141622 15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://www.mot.com/SPS/ JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC141622 16
MC141622/D MOTOROLA

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